What We Offer
- UVM Testbench components development, integration & maintenance
- VIP development, integration & debugging
- Functional & code coverage regression analysis
- Constrained-random test and sequence development
- SystemVerilog Assertions (SVAs) implementation
- Gate-level simulation (GLS) & timing analysis
- Formal Interconnectivity Verification
- Proven experience in SPI-based chips & Arm-Core multi-IP platforms
Οικονομικά στοιχεία εταιρείας
Στοιχεία Επικοινωνίας